1. Field of the Invention
This invention relates to integrated circuits, and more specifically to protecting an integrated circuit against electrostatic discharge while conserving power when the integrated circuit is connected in a system.
2. Description of the Prior Art
FIG. 1a illustrates an ESD portion of a typical integrated circuit, showing only the power conductors and a portion of the input/output section of the integrated circuit. Illustrated are several conventional input and/or output pads 10a, 10b which are only two of many such pads on a typical integrated circuit, for electrical connection to circuitry exterior to the circuit. Pads 10a, 10b are connected respectively to conventional input/output (I/O) logic circuitry 12a, 12b which respectively connects lines 14, 16 to the remaining portions of the integrated circuit (not illustrated here for simplicity). The power supply line 20 (the "upper rail") connects to voltage source V.sub.DD. Diode isolation line 32 (the "floating ESD rail") and upper ESD isolation diode 34 isolate the upper rail line 20 from the effect of transient signals on pads 10a, 10b detected by the trigger circuit. The "lower rail" line 22 connects to ground.
Diodes 24a, 24b, 18a, 18b provide ESD (electrostatic discharge) protection for respectively I/O logic 12a, 12b. N-channel shunt transistor 50 connects line 32 to the lower rail 22 for ESD protection. This protection, as is well known, operates as follows. ESD protection is provided when the integrated circuit (I.C.) is not connected in a system, i.e. typically after manufacturing of the I.C. and before installation of the I.C. in a system. It is well known that integrated circuits not yet installed in a system are subject to damage by ESD due to careless handling. A typical ESD event involves a fast rising static electric discharge which may rise from 0 volts to 2,000 volts and higher. So in this case, prior to installation in a system, both the upper rail 20 and the lower rail 22 are floating in terms of their voltage level.
The object is to drain the ESD to ground so that a minimum amount thereof flows into the I/O logic 12a, 12b, and hence only this minimal amount of charge passes to the remaining portions of the integrated circuit via lines 14 and 16. This is accomplished by a trigger circuit 42 (described in detail below) which provides an output signal to the gate terminal of the N-channel shunt transistor 50. Upon detection by the trigger circuit 42 of such an ESD event on line 32, a signal is provided by trigger circuit 42 which turns on transistor 50, hence shunting electrostatic charge from line 32 to ground line 22. The current path for such an ESD event at pad 10a is via line 32 to shunt transistor 50 to ground rail 22 to pad 10b. Thus the ESD is shunted through ground to pad 10b which protects the delicate circuitry of the integrated circuit. During this time the ESD protection diodes 18a, 18b, 24a, 24b are forward biased, so that only insignificant levels of the ESD current which is present at pads 10a, 10b takes any path other than through shunt transistor 50. That is, shunt transistor 50 provides considerably less impedance than the gates of the I/O circuitry. This charge is dissipated quickly enough (given a low shunt impedance) to protect the I.C.
The circuit of FIG. 1a has been found to work quite well for a typical ESD event encountered when the I.C. is a not connected in a system, i.e. pads 10a and 10b are not connected and hence are "floating". However, the trigger portion 42 of this circuit has been found deficient when the I.C. is installed in a system and hence pads 10a, 10b are connected to other integrated circuits or to other devices such as a bus connecting to another apparatus. This is because the trigger portion may trip on a rising transient at standard operating voltages, e.g. 5 V.
In this case, the problem arises when the I.C. illustrated in FIG. 1a is powered down so that lines 20 and 22 are both at a common ground potential and AC signals are applied to pads 10a and 10b from connected circuits (not shown) that transition above ground. Typically the trigger circuit 42 will be activated by these fast rising transitions which are erroneously detected as being ESD events. Since these in fact are standard operating voltage transitions e.g. 3.3 V, 5 V . . . , they pose no danger of damaging the integrated circuit. This problematically turns on the I.C. of FIG. 1a, causing current to flow at least momentarily during the duration of the trigger signal from line 32 to line 22 through shunt transistor 50. This shunting draws a large amount of current, for a period of time usually 1 .mu.s or longer, undesirably wasting power. This is primarily a problem with battery operated systems where power conservation is important.
The prior art trigger circuit 42 is shown in FIG. 2 where resistor 52 is connected to capacitor 54, with the node 58 between resistor 52 and capacitor 54 connected to inverter 56, the output terminal of which is connected to the gate of shunt transistor 50. The upper terminal of shunt transistor 50 is connected to line 32 (of the circuit of FIG. 1a).
This FIG. 2 circuit operates as a standard RC delay shunt enable circuit. After a sharp rising transient occurs on line 32 rising from the reference voltage to an applied voltage upper bias point, the node 58 will gradually rise towards the applied voltage. Immediately after the sharp rising transient, the node 58 voltage is below the inverter 56 low-transitioning trip point. Thus, the inverter is driving high (the applied voltage) to the gate of N-channel shunt transistor 50. The shunt transistor is now on and is shunting the applied voltage down to the reference node. This will cause a decay in the applied voltage (in the case of an ESD event). Eventually, a combination of the decay in the applied voltage and the changing potential of node 58 will cause node 58 to be above the low-transitioning trip point of inverter 56. This will force the output of inverter 56 low, to the reference voltage, and thus turn off the shunt transistor 50.
When the circuit in FIG. 2 is used as the trigger in FIG. 1a, its major disadvantage is that it can not be effectively used for ESD protection of powered down ICs interfacing with an active bus. The active bus may cause the trigger circuit to turn on the shunt, thus wasting power and potentially causing functional problems on the bus.
An alternate prior art solution (see FIG. 1b) to this problem is use of a Zener diode 59 for ESD protection connected between pad 10C and I/O logic 12C and to ground 22, with I/O output being on line 17, as an alternative to the circuit in FIG. 1a. However, use of Zener diodes is not compatible with many IC CMOS fabrication processes using lightly doped drains, due to current leakage or complete reverse breakdown at or below the standard operating voltage.
Thus there is a need for a trigger circuit which is reliably immune to tripping for fast bus transitions applied to a powered-down I.C. connected to the bus. The trigger circuit desirably would sense voltage but not consume DC current, either in the I.C. powered-up or powered-down modes and would be compatible with conventional CMOS IC fabrication processes.